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The SBS-1 System-Hardware

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System Overview
The Hardware:
CPU and Bus Structure The system is based on Intel 8085 microprocessor as its CPU. The lower byte of address is separated out from multiplexed data/address bus (AD0-AD7) by latching the lower byte of address in 8212 using the ALE signal from 8085. The upper byte of address is buffered by 74367. The output from 8212 and 74367 together constitutes the local address bus. The data from AD0-AD7 is buffered by two bi-directional bus drivers 8216. The output from two 8216 constitutes the local data bus the direction of the data bus is controlled by using the signals RD and INTA from the microprocessor when either of the signals is present, the local data bus will be pointing in i.e. towards the microprocessor is said to be in input mode.

  Reset On the board itself there is provision for power on auto reset. Reset button is also provided for manual reset. The RESET OUT signal from the microprocessor is buffered by 74367 and fed to various other integrated circuits on the board.

  Decoder The chip select signals for the ROM, RAM and other peripheral integrated circuits are derived by decoding the address bits A15 through A11 using 4 to 16 line decoder 74154. When address bit A15 is low the decoder 74154 is enabled and depending on the bit configuration of address bits A11, A12, A13 and A14 different devices are selected as follows…

A14
A13
A12
A11
Device Selected
0
0
0
0
EPROM1 (0000H-07FFH)
0
0
0
1
EPROM2 (0800H-0FFFH)
0
0
1
0
EPROM3 (1000H-17FFH)
0
0
1
1
Keyboard/Display controller (8279)
0
1
0
0
RAM1 (2000H-27FFH)
0
1
0
1
RAM2 (2800H-2FFFH)
0
1
1
0
RAM3 (3000H-37FFH)
0
1
1
1
Floating (may be used for any expansion)
1
0
0
0
Floating (may be used for any expansion)
1
0
0
1
Floating (may be used for any expansion)
1
0
1
0
Analog to digital converter (ADC0809)
1
0
1
1
Programmable interval timer (8253)
1
1
0
0
Programmable interrupt controller (8259)
1
1
0
1
UART (8251)
1
1
1
0
Programmable peripheral interface (right 8255)
1
1
1
1
Programmable peripheral interface (left 8255)


The processor board can support 6K bytes of Ram starting from location 2000H to 37FFH. Location starting from 20C0H to 20FFH is used by monitor programs. So the user should not use these RAM locations for their programs.


Restart Interrupts
  • RST 5.5 Dedicated to Keyboard/Display Interface (8279). 
  • RST 6.5 Available user interrupt. It is connected to the output pin 6 of TTL inverter 7400 (beside keypad). The user may apply interrupt request at the input of the inverter. The user should put JMP instructions and starting address of ISR routine from RAM location 20C8H. 
  • RST 7.5‘VECT INTR’ keyboard button interrupt. The user should put JMP instruction and starting address of RST 7.5 ISR routine from RAM location 20CEH. 
  • TRAPAvailable user interrupt. It is connected to the output pin 12 of TTL inverter 7400 (beside keyboard). The user may apply interrupt request at the input of the inverter. The user should put JMP instruction and starting address of TRAP routine from RAM location 20C0H. 
  • INTRConnected to the Programmable Interrupt Controller 8279



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